Throttling integrated link



Methods and apparatus for throttling an interface that is integrated on the same die as a processor are described. In one embodiment, a signal from an Integrated Input/Output hub (e.g., integrated on the same die as a processor) causes throttling of a link coupled between the IIO and an Input/Output (IO) device. Other embodiments are also disclosed.




Download Full PDF Version (Non-Commercial Use)

Patent Citations (9)

    Publication numberPublication dateAssigneeTitle
    US-2002033828-A1March 21, 2002Deering Michael F., Naegle N. DavidFlexible video architecture for generating video streams
    US-2004139283-A1July 15, 2004International Business Machines CorporationCache coherent I/O communication
    US-2004215371-A1October 28, 2004Samson Eric C., Aditya Navale, Puffer David M.Filter based throttling
    US-2005128846-A1June 16, 2005Broadcom CorporationMethods and circuitry for implementing first-in first-out structure
    US-2008162855-A1July 03, 2008Tessil ThomasMemory Command Issue Rate Controller
    US-5893153-AApril 06, 1999Sun Microsystems, Inc.Method and apparatus for preventing a race condition and maintaining cache coherency in a processor with integrated cache memory and input/output control
    US-6487689-B1November 26, 2002Lucent Technologies Inc.Receiver initiated recovery algorithm (RIRA) for the layer 2 tunneling protocol (L2TP)
    US-6721840-B1April 13, 2004Triscend CorporationMethod and system for interfacing an integrated circuit to synchronous dynamic memory and static memory
    US-6980024-B1December 27, 2005Altera CorporationI/O circuitry shared between processor and programmable logic portions of an integrated circuit

NO-Patent Citations (0)


Cited By (0)

    Publication numberPublication dateAssigneeTitle